1. Field of the Invention
The present invention relates to a Design for Test (“DFT”) technique which includes a scan architecture within an integrated circuit, and more particularly the present invention allows one to match bandwidth requirements of scan architecture, chip I/O, and an associated testing device. Moreover the present invention relates to techniques that can be utilized to reconfigure and support architectures that have various bandwidth requirements.
2. Description of the Related Art
Several Design for Test (DFT) techniques exist in Integrated Circuit (IC) testing, one of which involves implementing scan architectures on an IC. A scan architecture enables the ability to shift through any combinations of state values along with an ability to capture response(s) to the state values from elements within the IC. During testing of an IC, the scan architecture within the IC connects state elements in one or more scan chains. These scan chains, or shift registers, shift predetermined state values into the state elements in order to test a variety of possible inputs. After shifting the state values into the state elements, the IC returns to a normal functioning mode. One or more outputs (responses) are captured at the input(s) of the state elements. The IC then may enter a shift mode, which causes the captured response(s) to be shifted out of the IC and to a test device where the captured responses are compared with an expected output. If the captured response(s) match an expected output, then the IC may be functioning properly for the predetermined state value(s) shifted into the scan chains.
The current state-of-the-art for testing ICs, described with reference to FIG. 1, is to design a scan chain architecture 108 independently of a testing device's 106 capabilities. Within an IC 100 is the scan chain architecture 108 which includes a plurality of scan chains 102. The scan chains 102 are permanent and not configurable after the manufacture of the IC 100. The scan chains are basically shift registers which allow test data to be shifted into the IC 100 and out of the IC 100 when the IC is being tested. Generally, a test device 106 is electrically connected to the scan chains 102 allow for testing of the IC 100. Typically, the testing device 106 interfaces with available IC pins 104 to deliver test data to the scan chains 102 and extract the captured response(s) from the scan chains 102. The number of scan chains 102 implemented on the IC 100, as well as the latching frequency (scan chain's I/O frequency of operation), are designed based on the IC's physical constraints such as the number of pins 104, power consumption, and the operating frequency of the IC 100. Existing scan chain architectures determine the number of scan chains 102 to incorporate into an IC 100 by taking into consideration how may IC pins 104 can be used for scan chain interfaces. Furthermore, existing scan architectures design the latching frequency of the scan chains 102 to be much lower than the maximum possible I/O frequency of the IC 100. Once the number of scan chains 102 and the latching frequency are determined and the scan chain architecture is designed for and placed into the IC 100, these scan chain constraints and architecture cannot be altered.
A recent U.S. Provisional patent application described the idea of reconfigurable scan chains (U.S. Provisional Patent Application, Ser. No. 60/229,653) for reconfiguring the scan architecture to match the number of pins of a testing device. It is discussed that scan chains/segments can be cascaded using multiplexers to reduce the number of pins required for the scan interface. A drawback of the disclosed invention is that it does not take into account the frequency of the channels of the testing device to optimized the bandwidth across the interface between the testing device and the I/O of the integrated circuit (“IC”) being tested and between the scan chains and the I/O of the IC being tested.
The present techniques result in sub-optimal use of the available bandwidth between the IC I/O and the scan chains on the IC. Additionally, the scan chains are permanent fixtures that cannot be reconfigured or updated to coincide with updated test conditions or updated and advanced testing devices. Therefore, an IC may be rendered untestable by a testing device when test conditions or test devices are changed or modified. Furthermore, if an IC with a non-configurable scan architecture remains testable by an updated testing device or under updated test conditions, then longer test times or lower fault coverage may result.
The time required to test the IC and collect the response varies depending on, among other things, the number of available IC pins, I/O frequency of the IC, testing device frequency, and the amount of test data. For example, for a given test data volume, the test time is limited by the bandwidth (maximum data rate) of the IC, which is proportional to the product of the frequency and the number of test pins of the IC. The bandwidths of the integrated circuit testing device and the number of available test pins on the IC, as well as the scan chain architecture also limit the efficiency of an IC test. The testing device bandwidth limits how quickly the testing device can communicate test data to and from the IC pins. The bandwidth of the available IC pins limits how quickly test data is brought into the IC, and the latching frequency of the scan chains limit how quickly the scan chains latch in or latch out the test data.
Therefore, there is a need for a flexible scan chain architecture that has the capability of reconfiguring to one of various scan architectures based on the constraints of the IC and an associated testing device such that tests performed on an IC can be performed in a minimum amount of time with a high degree of accuracy and fault coverage.